Learning HDL

Hardware design languages (HDL) like VHDL and Verilog have significant benefits over high-level sythesis of hardware from C/C++ or graphical drag-and-drop interfaces.

HDLs do not execute sequentially, which means that every statement outside of certain constructs will execute almost at once.

There is not currently a open source synthesis tool, but they are license free. Typically you pay for specific IP. There are both license free and open source IDEs.

Simulation is nearly as important at synthesis.

VHDL

• VHDL is not case or white space sensitive
• Comments are prefixed with --
• Use parentheses liberally
• The VHDL synthesizer is picky about semicolons

if ... then
    ...
elsif
    ...
end if;

• Identifiers include variables, signals and ports
• There is no AND, OR or XOR
• A circuit is defined by a entity, which includes the definition of its interface to other circuits, which consists of signals that may be in, out or inout and a data type (e.g. std_logic)
• The structure inside the entity is referred to as a architecture
• More than one port can be associated with a signal
• std_logic_vector allows you to bundle signals
  • The order in a bundle is specified using to or downto
  • downto is big-endian, while to is little-endian
• library IEEE; use IEEE.std_logic_1164.all; allows 9 different signal values including 0, 1, U, X, Z W, L, H, -
• bit can only be 0 or 1
• use IEEE.numeric_std.all; imports a library for unsigned type and various arithmetic operators
• Circuits are modeled in four ways: data-flow, behavioral, structural and hybrid
• Three frequently used architecture object types are the signal, variable and constant
• Signals are declared before the begin keyword, and are assigned using <=
• Variables are declared in a process construct, and are assigned using :=

architecture circuit_1 of <entity-name> is
    signal sig_1 : std_logic;
begin
    process (a,b,c)
        variable var_1 : integer;
    begin
        port_f <= not (port_a and port_b and port_c);
        sig_1 <= port_a;
        var_1 := 34;
    end process;
end circuit_1;

• Assignments to signals are slower than to variables
• The process construct provides sequential execution of statements, but the process itself is concurrent

See also

• AXI Cheatsheet
• Xilinx AXI DMA and VDMA
• FPGAs Have the Wrong Abstraction