Hardware design languages (HDL) like VHDL and Verilog have significant benefits over high-level sythesis of hardware from C/C++ or graphical drag-and-drop interfaces.

HDLs do not execute sequentially, which means that every statement outside of certain constructs will execute almost at once.

There is not currently a open source synthesis tool, but they are license free. Typically you pay for specific IP. There are both license free and open source IDEs.

Simulation is nearly as important at synthesis.

VHDL

if ... then
    ...
elsif
    ...
end if;
architecture circuit_1 of <entity-name> is
    signal sig_1 : std_logic;
begin
    process (a,b,c)
        variable var_1 : integer;
    begin
        port_f <= not (port_a and port_b and port_c);
        sig_1 <= port_a;
        var_1 := 34;
    end process;
end circuit_1;